
module TemporalMixer(
  input  wire       clk,
  input  wire       rst_n,
  input  wire       clken,
  input  wire [4:0] slot,
  input  wire [1:0] stage,
  input  wire       rhythm,
  output reg  [4:0] maddr,
  input  wire [9:0] mdata,
  output reg  [9:0] mo,
  output reg  [9:0] ro
);

reg mmute;
reg rmute;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        maddr <= #1 5'b0;
        mmute <= #1 1'b1;
        rmute <= #1 1'b1;
    end
    else if(stage==2'd0)begin
        if(!rhythm)begin
        case(slot)
        5'd0: begin
                  maddr <= #1 5'd1;
                  mmute <= #1 1'b0;
              end
        5'd1: begin
                  maddr <= #1 5'd3;
                  mmute <= #1 1'b0;
              end
        5'd2: begin
                  maddr <= #1 5'd5;
                  mmute <= #1 1'b0;
              end
        5'd3: begin
                  mmute <= #1 1'b1;
              end
        5'd4: begin
                  mmute <= #1 1'b1;
              end
        5'd5: begin
                  mmute <= #1 1'b1;
              end
        5'd6: begin
                  maddr <= #1 5'd7;
                  mmute <= #1 1'b0;
              end
        5'd7: begin
                  maddr <= #1 5'd9;
                  mmute <= #1 1'b0;
              end
        5'd8: begin
                  maddr <= #1 5'd11;
                  mmute <= #1 1'b0;
              end
        5'd9: begin
                  mmute <= #1 1'b1;
              end
        5'd10: begin
                  mmute <= #1 1'b1;
              end
        5'd11: begin
                  mmute <= #1 1'b1;
              end
        5'd12: begin
                  maddr <= #1 5'd13;
                  mmute <= #1 1'b0;
              end
        5'd13: begin
                  maddr <= #1 5'd15;
                  mmute <= #1 1'b0;
              end
        5'd14: begin
                  maddr <= #1 5'd17;
                  mmute <= #1 1'b0;
              end
        5'd15: begin
                  mmute <= #1 1'b1;
              end
        5'd16: begin
                  mmute <= #1 1'b1;
              end
        5'd17: begin
                  mmute <= #1 1'b1;
              end
        endcase
            rmute <= #1 1'b1;
        end
        else begin
        case(slot)
        5'd0: begin
                  maddr <= #1 5'd1;
                  mmute <= #1 1'b0;
                  rmute <= #1 1'b1;
              end 
        5'd1: begin
                  maddr <= #1 5'd3;
                  mmute <= #1 1'b0;
                  rmute <= #1 1'b1;
              end 
        5'd2: begin
                  maddr <= #1 5'd5;
                  mmute <= #1 1'b0;
                  rmute <= #1 1'b1;
              end 
        5'd3: begin
                  maddr <= #1 5'd15;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd4: begin
                  maddr <= #1 5'd17;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd5: begin
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b1;
              end 
        5'd6: begin
                  maddr <= #1 5'd7;
                  mmute <= #1 1'b0;
                  rmute <= #1 1'b1;
              end 
        5'd7: begin
                  maddr <= #1 5'd9;
                  mmute <= #1 1'b0;
                  rmute <= #1 1'b1;
              end 
        5'd8: begin
                  maddr <= #1 5'd11;
                  mmute <= #1 1'b0;
                  rmute <= #1 1'b1;
              end 
        5'd9: begin
                  maddr <= #1 5'd14;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd10: begin
                  maddr <= #1 5'd16;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd11: begin
                  maddr <= #1 5'd13;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd12: begin
                  maddr <= #1 5'd15;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd13: begin
                  maddr <= #1 5'd14;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd14: begin
                  maddr <= #1 5'd16;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd15: begin
                  maddr <= #1 5'd13;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd16: begin
                  maddr <= #1 5'd16;
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b0;
              end 
        5'd17: begin
                  mmute <= #1 1'b1;
                  rmute <= #1 1'b1;
              end 
        endcase
        end
    end
end


always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        mo <= #1 10'b0;
    else if(stage == 2'd0)
        mo <= #1 10'h200;
    else begin
        if(!mmute) begin
            if(!mdata[9])
                mo <= #1 10'h200 + {1'b0, mdata[8:0]};
            else
                mo <= #1 10'h200 - {1'b0, mdata[8:0]};
        end
        else
            mo <= #1 10'h200;
    end
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        ro <= #1 10'b0;
    else if(stage == 2'd0)
        ro <= #1 10'h200;
    else begin
        if(!rmute) begin
            if(!mdata[9])
                ro <= #1 10'h200 + {1'b0, mdata[8:0]};
            else
                ro <= #1 10'h200 - {1'b0, mdata[8:0]};
        end
        else
            ro <= #1 10'h200;
    end
end


endmodule
